IEEE Design & Test
March/April 2003
http://computer.org/dt/


Features

Guest Editors' Introduction: Board Test
Monica Lobetti-Bodoni and R.G.(Ben) Bennetts

Minimizing Pattern Count for Interconnect Test under a Ground Bounce
Constraint
Erik Jan Marinissen, Bart Vermeulen, Henk Hollmann, and R.G.(Ben) Bennetts

Embedded Boundary
Scan Bradford G.Van Treuren and Jose M.Miranda

Electromagnetic Signatures as a Tool for Connectionless Test
Mahnaz Salamati and Dag Stranneby

Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal
Test
Uro .s Ka .c, Franc Novak, Florence Azais, Pascal Nouet, and Michel
Renovell

Special Features

Fast Fault Simulation for Nonlinear Analog Circuits
Nur Engin and Hans G. Kerkhoff

A Design-for-Verification Technique for Functional Pattern Reduction
Chien-Nan Jimmy Liu, I-Ling Chen, and Jing-Yang Jou

Efficient System-Level Functional Verification  Methodology for Multimedia
Applications
Miroslav Cupak, Francky Catthoor, and Hugo J. De Man

Compilation for FPGA-Based Reconfigurable Hardware
Joao M.P.Cardoso and Horacio C. Neto

Departments

EIC Message

Roundtable

Conference Reports

Panel Summaries

DATC Newsletter

TTTC Newsletter

The Last Byte

The May-June 2003 issue of D&T will feature a special issue on Power-Supply
Design and Analysis for ICs, a follow-up special section on last-year's
Infrastructure IP issue, plus some exciting pre-DAC coverage.
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